A Low Power High Efficiency Unified Cache IP Design with AHB-AXI Bus Interface

As the bridge between CPU and system bus, Cache is the major power consumption source of the chip.Power efficient cache design is of great importance.And traditional cache design is lack of flexibility to integrate into different systems.A low power AHB-AXI double bus unified Cache design is proposed to reduce Cache access times and improve off-chip memory access efficiency.The test result shows that the design can notably reduce cache power consumption and improve system overall performance.