Design and realization of TMR error correction system based on SOC

Aiming at the problem that DDR cache of SOC devices used in the aerospace field is easy to generate data errors in the space application environment, this paper designs and implements a three-mode redundancy error correction system to ensure the accuracy of DDR cache data in the space application environment. The system carries on the three-mode redundancy voting through the hardware circuit form, and writes the voting result back DDR corresponding cache address space. It not only reduces the CPU resource, but also increases the voting speed. In this design, a feedback error correction mechanism is proposed, which is different from the general three-mode redundancy, which can tolerate but not correct errors, and can quickly and in batches correct errors. It is verified through XC702 development board of Xilinx company. After the DDR of the development board is injected with error data, this design can successfully carry out the system fault tolerance and correct the error data of the source address on the development board. The accuracy of the SOC device DDR cache is ensured.