The Design of Low Power Dissipation Pipeline ADC in CCD Image Processor

This paper presents design of a 10bit and 90 Ms/s pipeline ADC which is used in CCD image processor. Using Dynamic Comparator and omitting the input stage S/H (Sample and Hold), the ADC achieved the characteristic of low-power dissipation. The designed ADC is implemented in Charter 0.35μm 2P4M CMOS process technology. Simulating results indicate that it can achieve an ENOB (Effective number of bit) of 9.3 bit, a maximum DNL of 0.5 LSB, a maximum INL of 0.8 LSB for a 3.3MHz sinusoid input at 90MHz sampling rate. The total power consumption of the ADC core is only 35.4mW from a 3.3V supply.