Clock Tree Topology Optimization Based on Reconstructing Subtree Topology for 3D Ics

The traditional TSV-based 3D clock tree synthesis (3D CTS) flow mainly concludes abstract topology generation, embedding, routing and buffering. The classic 3D clock tree abstract topology generation algorithms ignore the adjustment for the generated topology after the first step. In this paper, we propose a clock tree topology optimization algorithm, the LMOR algorithm, for reconstructing the structure of some specific subtrees in the generated 3D clock tree abstract topology and relocating the position of the roots of these subtrees. The simulation results show that the total wirelength and delay can be reduced by up to 4.56% and 14.67%.