A 10 bit 125 MS/s Zero Crossing Detection Pipeline-SAR ADC Based on 45 nm SOI CMOS Technology

A two-stage pipeline-SAR ADC is designed in this paper based on 45nm SOI CMOS technology. A zero crossing comparator and controlled current source are used to replace the power-hungry OTA to achieve residual amplification, which reduces the power consumption of ADC greatly. The impact of comparator offset on ADC resolution is analyzed, and a dynamic comparator with calibration is proposed to meet the requirement of high resolution and high speed. Besides, in the design of successive approximation structure, the power is further reduced by adopting common-mode switching, top-plate sampling and full custom control logic. Simulation results show that the signal to noise distortion ratio, spurious free dynamic range and effective number of designed ADC are 60.46 dB, 77.33 dB and 9.75 bit, respectively, at 125 MS/s with Nyquist input frequency. The ADC consumes only 1mW and obtains a much smaller figure-of-merit of 9.29fJ/step comparing with other state of arts.