Physical and Timing Modeling of DAC IP Core Based on 40 nm CMOS Process

Based on 40 nm CMOS process, the necessary information needed for transforming DAC module into IP core is analyzed, and the main characteristics of reusable models for DAC IP core are outlined. The physical model and timing model of DAC IP core are obtained by modeling the physical and timing information, which are used to form the data file deliveries. The abstracted models can protect the design details, and can meet requirements for basic application, such as place and route, timing analysis.