Design and implementation multiplier based on new booth selector and compressor

In order to optimize the multiplier critical path delay and reduce the circuit area, improve the overall performance of the multiplier. Based on the Radix 4 booth algorithm, this paper proposes a new type of booth selector for the problem of partial product generator delay, which is used to improve the efficiency of partial product generation. At the same time, this paper proposes a new type of 4-2 partial product compressor to improve the compression efficiency of the partial product compressor. Based on the tsmc 28 nm process, the signed 16-bit multiplier using the above optimization points is simulated and synthesized. The critical path delay of the multiplier designed in this paper is 0.98 ns. The experimental results show that the two new designs proposed in this paper can improve the computational performance of the multiplier.