TAO Yu-liang, HE Wei-feng, WANG Qin, MAO Zhi-gang, LI Yong-wei, ZHENG Ji-jun. A VLSI Architecture and Application for Multi-Standard Macro-block Prediction and Boundary Strength Calculation[J]. Microelectronics & Computer, 2011, 28(6): 26-30.
Citation: TAO Yu-liang, HE Wei-feng, WANG Qin, MAO Zhi-gang, LI Yong-wei, ZHENG Ji-jun. A VLSI Architecture and Application for Multi-Standard Macro-block Prediction and Boundary Strength Calculation[J]. Microelectronics & Computer, 2011, 28(6): 26-30.

A VLSI Architecture and Application for Multi-Standard Macro-block Prediction and Boundary Strength Calculation

  • In this paper, a VLSI architecture is proposed for macro-block prediction and boundary strength calculation which supports H.264 (High Profile 4.1) and AVS (JiZhun Profile 6.0) video decoder.The control-dominant algorithms, intra mode prediction, motion vector prediction and boundary strength calculation in H.264 and AVS are implemented by this architecture that can be applied to the current reconfigurable multi-media systems.After design implementation, the work frequency can be up to 312MHz at TSMC 65nm technology library.The number of maximum cycles to decode one H.264 and AVS macro-block is 351 and 189 respectively, which meets the requirement of real-time processing for H.264 and AVS High Definition (1080p) .
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