Design and Implementation of Embedded GPU Cache Controller

A suitable for embedded GPU cache controller is designed for the speed mismatch problems data interaction between main memory and embedded GPU. The cache controller adopts a four-way set associative mapping structure, uses pseudo-Least Recently Used replacement algorithm. The size of CacheSRAM can be configured, which configuration range is 32~512 kB. The experimental results show that when the CacheSRAM capacity is 128 kB, hit rate of the graphics application's Cache can reach to 71.12%, the cache controller can further enhance the overall performance of embedded GPU.