High Performance VLSI Architecture for HEVC Motion Estimation

High Efficiency Video Coding(HEVC) is the next generation video coding system under standardization.HEVC employs the Largest Coding Unit(LCU) up to 64×64 pixels with Asymmetric Motion Partitions(AMP),which significantly increases the algorithm complexity of Motion Estimation(ME).In this paper,a novel VLSI architecture compatible to HEVC ME algorithm is proposed for the first time.A quarter of LCU size's Processing Element(PE) array architecture is adopted to conduct full search ME with 849 different block sizes from 4×4 to 64×64 pixels,168 AMPs such as 4×16 and 24×32 pixels,as well as 3 search ranges(SR) including -4,4),-8,8) and -16,16) pixels.Moreover,a hierarchy data reuse scheme and a memory access strategy are adopted to reduce off-chip bandwidth up to 99.2% compared to the traditional method.Using TSMC 90 nm 1P9M technology,the proposed architecture is synthesized at the maximum work frequency of about 330 MHz with 860×10³ Gates and 229 mW.Simulation results show that the architecture is able to process 3 840×2 160 p video at 30 f/s at nearly 280.4 MHz.