An Adaptive Negative Bit-Line Voltage Scheme for Improving Write-Ability of SRAM

With the feature size falling into nano-scale,the increased process variation degrades write-ability of SRAM cells in the process of producing SRAM.To solve this problem,a novel negative bit-Line voltage scheme is presented to improve write-ability of SRAM cell.With controlling timing and the gate voltage of pull-down transistor,the negative voltage can be self-adjusted and suppressed in a certain range.The result is verified by using TSMC 40nm process model.The result shows that the write-ability can be improved by the newly designed circuit.SRAM even can operate normally at 0.66V.As the voltage increase,the negative voltage is suppressed in a certain range,which can improve the using life of transistors and the product yields.