CHEN Liang, LI Yan, LI Ming, YU Fang, LIU Zhong-li. Improvement of Place and Route for an Island-Style FPGA[J]. Microelectronics & Computer, 2012, 29(8): 19-23.
Citation: CHEN Liang, LI Yan, LI Ming, YU Fang, LIU Zhong-li. Improvement of Place and Route for an Island-Style FPGA[J]. Microelectronics & Computer, 2012, 29(8): 19-23.

Improvement of Place and Route for an Island-Style FPGA

  • A place and route tool VA is exploited for an island-style FPGA VS1000 architecture.It makes two improvements on the basis of VPR.Firstly, global signal routing resource graph based on routing resource graph of traditional routing algorithm was established.Global signal routing was completed in order to separate global signal routing and common signal routing for the purposes of reducing relative delays of global signals and saving common routing resource.Secondely, this research proposes two new route orders: high fanout priority and high criticality priority.Experimental results show the iterations can be reduced by 21.8% on average under high fanout priority order, the critical path delay can be reduced by 22.3% on average under high criticality priority order.
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