Code compression technology for processors based on RISC-V instruction set architecture

Aiming at design and verification problems caused by the exponential growth of the code size in the embedded system processors, the Bitmask-based code compression technology for processors based on RISC-V instruction set architecture is presented. Based on the features of RISC-V instruction set, a Bitmask-based code compression algorithm combined with mixed encoding and separate dictionary is designed. Without affecting the processor structure and Cache working mechanism, a simple and efficient hardware decompression unit is designed to reduce the program memory space required by the embedded system processor. Mixed encoding format for RISC-V instruction set is used to reduce the length of the original instruction, which improves the code compression rate. Besides, two separated dictionaries are used to obtain a small hardware decompression delay without affecting the code compression rate. The experimental results show that the code compression ratio is 61.1% on average without much hardware overhead on the RISC-V instruction set architecture, which greatly reduces the program memory space required by the processor.