Design and implementation of FPGA-based real time multiple face detection system

A small and high-precision face detection algorithm based on MobileNetV2-SSDlite is designed. To improve the computing capability of mobile terminals, the study of the mobile algorithm specific neural network accelerator is carried out in terms of hardware architecture, on-chip memory, performance and power consumption. A real-time multi-face detection accelerator system is simulated and implemented on ALINX AX7350 SOC platform. The results show that under a 100MHz clock, the face detection system has an average computing performance of 56.01 GOPS and a power consumption of 7.3W. Compared with the existing MobileNetV2-SSDlite accelerator, the operation speed is improved by 28.7%, the resources are reduced by 44.46%, and the power consumption is reduced by 26.3%. The speed of the system in inferencing a 224×224 resolution picture reached 83.4 FPS, meet the demand of real-time performance.