Design of 6.25 Gb/s SerDes Receiver

In this paper, a 65 nm CMOS 6.25 Gb/s SerDes receiver is designed. Equalization is achieved by using continuous-time linear equalizer. The sampler employs a novel sense amplifier(SA), which improves the sensitivity by the conventional SA of magnitude and simultaneously solves the problem that falling edge lags rising edge the time of a gate delay; a half-rate second order clock and data recovery system is presented. Simulation results show that the receiver has the correct logic function, the power consumption is 10.2 mW.