Design of High Resolution Comparator for 16 Bit SAR ADC

This paper presents a low noise low offset comparator used in a 1 MSPS 16 bit successive approximation register analog to digital converter (SAR ADC). The comparator is composed of five stages preamplifier and a regenerative latch. The output offset storage technique is used to further reduce offset voltage. In the design of 16bit SAR ADC, RMS noise becomes another key factor restricting the resolution. A novel bandwidth optimization method for preamplifier stages is used to achieve lower noise and lower power consumption. Implemented in TSMC 0.18 μm CMOS technology and simulated in Cadence Spectre, the proposed comparator achieves low RMS noise of 16 μV and low offset standard deviation of 5.8 μV with 3.4 mW power consumption, satisfying the stringent requirement of 16 bit SAR ADC.