Design of a High Performance Output-Capacitorless LDO

A High Performance Output-Capacitorless LDO is presented in this paper. In this design, EA applies a push-pull output amplifier, so that it can maintain low power consumption in quiescent state, and provide large output current in the transient response, which greatly improve the response rate. High loop gain allows the LDO circuit to achieve very high regulation accuracy; and using zero compensation technology to enhance the stability of the LDO loop. The LDO is designed in 0.13 μm CMOS process. Simulation results show that the output voltage can be stable at 1.0 V when its supply is range from 1.2 V to 2.0 V. The output load current is from 50uA to 100 mA, the maximum load capacitance is up to 100 pF, PSR at low frequency is -67.5dB@100mA~-85.5dB@50μA. Load regulation is 0.8μV/mA. The LDO only consumes 50 μA quiescent current, and the overall layout area is 0.0163mm².