The Design and Implementation of Vector Generation Based on JTAG

With intensive study on IEEE std l149.1, by using the basic idea of HT (Half Transition, HT) fault mode1. a new reordering vectors of HT fault model is proposed, and an architecture for signal integrity test based on extended JTAG is designed and realized. The implementation of the idea is that, to fully comply with IEEE 1149.1 standard, one new instruction have been added to extend the function of boundary-scan architecture and provide the support to SI testing.