Design of a 2.45 GHz High Linearity CMOS Power Amplifier

A 2.45 GHz high linearity and low power CMOS power amplifier (PA) with capacitance compensation is designed in this paper, which uses differential constructor and works in class of AB. The driver stage uses common source common gate architecture to provide large output voltage swing for the next stage, and the power stage uses common gate architecture with LC resonance as load impedance to provide large output power. Besides, the PA is optimized from MOSFETs, and PMOS capacitance compensation is raised to enhance linearity and realize low power through compensating the gate-source capacitance (C_gs) and decreasing the third-order inter-modulation distortion (IMD3) by 10 dBc. The proposed PA is designed and simulated on the basis of TSMC 0.18 μm RF CMOS process. Simulation results show that the PA's reflection coefficient is less than -20 dB, power gain is 25dB, power-added efficiency(PAE) is 27%, and the third-order inter-modulation distortion (IMD3) is less than -42dBc at 2.45 GHz.