Low Power Data Cache Design Based on Load Reuse

Data cache consumes a large amount of energy in embedded processor. This paper proposes a low power design method of data cache based on load reuse to save the data cache power consumption. The load reuse unit saves the loaded data from the data cache and the saved data could be reused by later loads. This approach can reduce a majority of data cache accesses, thus saving the data cache power consumption significantly. Experimental results of SuperV_EF01 DSP show that, in comparison with traditional data cache, this approach could save 29.48% of data cache power consumption, with only 0.64% of data cache area increasing and no performance degradation.