Design of CAM Controller in High Performance Routers

Content Addressable Memory is widely used in high performance routers since the excellent skill of looking up data in the routing table. According to the specification of the CAM, this thesis designs an architecture of CAM controller. The controller can control 8 independent blocks of CAM, each block has an ID, the searching operation can be executed in the blocks which have the right ID. The result of the searching operation provides the highest priority match address. The pipeline technique is used to control 8 block of CAM. Only one nop instruction is needed between searching operations, the speed of searching is very fast.