HLS-based design and optimization methodology for convolutional neural network

Based on High Level Synthesis (HLS) design methodology of FPGA, this paper implements a convolutional neural network accelerator on ZYNQ-7020. The design method of cyclic unroll and pipelinling is used to optimize the convolution kernel operation, and the occupied logic resources and operation efficiency are balanced to achieve the optimal performance of the accelerator. The performance of the accelerator is tested by the MINST dataset at 100MHz working frequency. The results show that:the accelerator can achieve 3.77 times acceleration compared to the general platform ARM A9for a single picture, and the streaming processing of thousands of pictures can achieve up to 6.14 times acceleration.