VLSI Design of Router for Network on Chip

A router with 3-stage pipeline architecture is designed for network on chip (NOC) in this paper.It is used wormhole forwarding strategy and deterministic routing algorithm and supports both Mesh and Torus topology.In order to increase throughput, the virtual channels technology is also used.The NOC router is implemented on Xilinx Virtex2p XC2vp30 with a maximum clock frequency of 130MHz and transmission bandwidth of 20.8Gb/s.