A 1.6GHz Highly Linear and Efficient Driver Amplifier Design

This paper presents the design of a driver amplifier for 1.6 GHz navigation transmitter application based on 0.35 μm RF CMOS process.In this work, a two-stage topology is proposed.The first stage employs two parallel transistors working in class AB and B mode respectively to improve the linearity and efficiency of the driver.The second stage utilizes a class AB common source amplifier to further increase the performance.The simulated results exhibit a maximum OIP3 of 17.3 dBm, a PAE of 57%, a saturated output power of 18.5 dBm, a power gain of 26 dB with a total dc current consumption of only 5.4 mA from a voltage supply of 3.3 V.