A Single-Event Hardened Phase-Locked Loop Design Based on PDSOI CMOS Process

Based on the 0.35 μm PDSOI CMOS process,a normal phase-locked loop with a frequency range of 700 M Hz to 1.0 GHz is designed.By using Sentaurus TCAD,the radiation sensitivity parts have been identified.A radiation-hardened by design phase -locked loop is proposed by presenting a current limited circuit and by using multiband VCO structure to reduce the VCO gain.The simulation results show that the wave peak of VCO control voltage Vc,the recover time,the error pulse numbers reduced to 43.9%,49.7% and 29.1% compared with the normal one. The difference of VCO structure between the single-event-hardened PLL and normal one is not signifant,so the wave peak of VCO control voltage Vc,the recover time of PLL and the error pulse numbers of output signal are not signifantly changed.