Non-Idealities Modeling and Verification of Σ-Δ Modulator

Σ-Δ modulator is a common used critical part in mixed signal circuits. In this paper, based on a second order low-pass modulator, all the non-idealities are analyzed and modeled including non-ideal switch, colored noise model, non-linear DC gain and multi-bit DAC capacitor mismatch, which are not included together in existing work. The modulator is implemented in HJTC 0.18μm process with taping out and test has been accomplished. Modulator model is verified through compare with circuit simulation and actual circuit measurement data. The presented modeling method serves as an accurate and efficient guide for architecture and modulator circuit design.