A FPGA accelerator to compute image euler number

Euler number is an important feature of a binary image. Now, this paper proposes an efficient FPGA accelerator to improving the current computing efficiency which is designed for computing the Euler number based on the Euler Method of Gray System Model, according to the Euler theorem in the graph theory. Making good use of the parallel processing capability of FPGA, adopting design of three stage pipeline, the speed of FPGA accelerator computing the Euler number is improved greatly. The random 41 noisy binary images tests turn out that processing time of the advanced algorithm in PC is sensitive to the target pixels density change and the slowest is five times slower than the fastest. However, processing a image in FPGA accelerator is no concern with pixels density and low power depletion fast as read a image in theoretically, which is 20 times faster than advanced algorithm in PC.