A high-efficiency cache SEU fault tolerance method using bit selective placement and extended-FastTag

Cache in the space application processor has always been a vulnerable spot in radiation-hardened design, which leads the Cache of domestic devices cannot be used in orbit. Cache stores the frequently used instructions and data, and the radiation-hardened effect of Cache directly determines the capability of anti-SEU of the space application processor. Tag Array is an important part in Cache, traditional SEC method used in which can only correct single bit error, and double adjacent bits error may cause false correction. What's more, it will cause a large area and power overhead when used in set-associative and full-associative Cache. This paper designs an energy-efficient Cache Tag fault-tolerant method, which combines bit selective placement strategy and extended-FastTag. The proposed has three characteristics: (1) Extend the traditional FastTag technique to write-back Cache. (2) Improve the detection rate of double adjacent error with the same code redundancy rate compared to traditional SEC. (3) Reduce the area and power overhead caused by fault tolerance compared to traditional SEC. By simulation and evaluation, the energy efficiency ratio is improved compared to the traditional SEC method. The adjacent double error detection rate can be increased about 70%, and the area overhead is reduced by 12.1%, and the power consumption overhead is reduced by 47.6%, and the critical path delay is reduced about 0.2ns.