Design of a Current-Steering DAC IP Core Based on 40 nm CMOS Process

Based on SMIC 40 nm CMOS process, a 10 bit 100MS/s DAC IP core was designed. A 6+4 segmented current-steering architecture was employed in the DAC IP core, and the full-scale output current was 20 mA with 1.1 V/2.5 V dual power supplies. For the DAC IP core, the prototype design of circuit and layout was completed, and the physical model and timing model were obtained to form the data deliveries. The simulation analysis of the DAC IP core was carried out, and the test results after tape-out were presented.