Design and implementation of 8B/10B parallel coding circuit for JESD204B protocol

This paper designs and implements a four-way parallel 8B/10B encoding circuit, which has been verified by NCVerilog simulation. It can work at 405 MHz under a 65-nm technology library, supporting 16.2 Gbps serial data transmission rate, occupying 1832μm² of logical resources. As the 8B/10B coding module in JESD204B protocol, it has been applied in the SerDes interface circuit of a high-speed ADC chip. The actual circuit test shows that the encoder meets the 12.5 Gbps maximum transmission rate requirement of JESD204B protocol standard.