Sub-picosecond level clock jitter measurement technique based on ADC noise distribution

For the affection of clock jitter on signal-to-noise ratio (SNR), a novel technique of measuring sub-picosecond level clock jitter based on ADC noise distribution is proposed. By modeling the sampling error of ADC, the mathematical formula of sampling error caused by clock jitter was observed. It also presented the highest frequency of sampled signal limited by SNR. For the different determinant of sampling noise, the measure of sub-picosecond level clock jitter by two frequency sampling was observed. All the conclusions were verified by simulation and test. The results show the test error is less than 10fS in clock jitter measurement up to a signal frequency of 1.6GHz, which indicated that the proposed method had a characterization of easy operation and high resolution.