Design and Implementation of 2D Graphics Accelerator

This paper designs and implements the 2D(2 Dimensional) Graphics Accelerator circuit.It provides the basic primitives point,line,polygon,and displays the words with any size and color.A pipeline architecture is used in the design.To exchange information handshake signals is used between the pipeline stages.It not only shortens the processing time and improves work efficiency,but also facilitates the co-ordination of the timing between the various sub-modules.The paper studies two kinds of high-frequency algorithms,uses the Verilog HDL language to describe 2D Graphics Accelerator hardware circuit.Compared with the simulation results of the behavior model,which is built by SystemVerilog,the results are consistent,and implements on FPGA.The operating frequency can reach 205 MHz with SMIC 0.13 μm standard CMOS cell library.