A fast and efficient compiler framework for CGRAs

This paper provides a hardware and software co-design technique to optimize the compilation time and area efficiency of loop acceleration on Coarse-Grained Reconfigurable Architectures (CGRAs). From the hardware prospective, the architecture of each processing element (PE) is optimized by replacing register file within PE with bypass logic. On the software side, we develop a novel and efficient loop mapping algorithm, which greatly shrinks the search space for the optimal solution. The iteration of forward greedy placement and backward recovery obtains a fast and stable compile speed and guarantees performance close to the optimal solution.This hardware and software co-design method improves the area and computation efficiency. Experiment result shows that our framework improves1955xin compile speed and obtainsa 1.25x area efficiency.