A Novel Equalizer Circuit for High-Speed Interface Circuit

This paper presents a new type of high-speed equalization circuit.On the basis of the traditional source degeneration equalization filter,a new equalization circuit structure is proposed.The circuit performance is greatly improved with the advantages of active inductor and symmetric load structure.Without using on-chip inductors,the new structure optimizes the circuit,saves chip area,while alleviates the speed bottleneck of the traditional equalization circuit.Judging by simulation results,the high frequency compensation gain of the equalizer circuit is up to 17.2dB,meanwhile,the ratio of high frequency to low frequency is 5.24.The circuit operates functionally when signal speed rates up to 5Gbit/s.The circuit topology is simple,and applicable to a variety of high-speed interface circuit.This chip is realized in 0.13μm CMOS process.