Design and Implementation of a Decimation Filter for ΣΔADC

A kind of design method and hardware realization about the digital decimation filter used for high resolution ΣΔ ADC is introduced.An improved design method which has 10% hardware saving compared to tradition architecture is proposed.With a new structure named series-parallel structure which is used in half-band filter, the last stage of the decimation filter will has 50% hardware saving.In the trade off between area, power consumption and speed, with the methods of CSD (canonic signed digit), CSE (common sub-expression elimination), Poly-phase Decomposition and the new series-parallel structure proposed here, we implemented a low power and area decimation filter.The filter whose area is 0.59mm2 is implemented in 0.18μm CMOS process and has 18% less hardware.