An Implementation of Decimation Filter Based on FPGA

This paper proposes a decimation filter structure,which is implemented in FPGA with CIC decimation filter and CIC compensation filter.This structure is based on the idea of trading time for space.It has greatly reduced the number of hard -nucleus multipliers.Besides,it takes advantage of the characteristics of FPGA's resource distribution,and has proposed a way to use embedded RAM.It has reduced the cost of logic elements and optimized the allocation of resources.Good filtering performance has been got with the most reasonable cost of resources.