Optimization in physical design of 3 200 Mbps DDR4 PHY

The physical design and its optimization were proposed for the DDR4 PHY of one High Performance Computing chip based on TSMC 16 nm FinFET process technology, including the floorplan、placement、clock tree synthesis and its optimization and timing closure analysis. Take macros and IO cells combined with area and timing optimization into account to fix the floorplan shape of DDR4 PHY. Compare the typical CTS with optimized MSCTS and analyze their differences when clock tree synthesis. Design multi-bit buffer M2M8 for DDR4 PHY whose drive distance can be 1200 μm. Simulation results show that optimized clock tree structure level decreases from 65 to 19, max clock latency decreases by 48.37%, clock skew decreases by 52.33%, power decreases by 17.24%, the performance optimization results are prominent and achieve the goal of experiment.