Design of Grouped and Mixed Parallel Arbiter for NoC

A grouped and mixed parallel arbitration strategy is proposed in this paper which is suitable for two-dimensional or three-dimensional network-on-chip. The strategy groups input requests so as to process with them in parallel computing and assimilates the advantages of matrix and round robin arbitration strategy. Based on the new strategy, two grouped and mixed parallel arbiters are proposed and implemented in Verilog HDL with better performance such as delay, maximum working frequency and chip area.