Design and analysis of the all-digital phase-locked loop based on adaptive loop filtering algorithm

The digital Loop filter is a key module in all digital phase locked loop (ADPLL) and has an important impact on the performance of the loop. In order to shorten the settling time and reduce the in-band phase noise, this paper proposes a type Ⅱ ADPLL adaptive loop filtering algorithm. To implement the algorithm, several sets of loop filter parameters with large to small bandwidth are pre-selected. In the tracking process, the algorithm will switch those parameters orderly at a special time according to the state of the loop, and the non-ideal jump of frequency control word caused by the switching is compensated at the same time. Finally, this paper built a Type Ⅱ ADPLL with three sets of loop filtering parameters in HSPICE using Verilog-A language, and simulated the algorithm. The simulation results show that the total lock time of the loop is only slightly larger than that of the first set of parameters, and the phase noise characteristic after locking is the same as the last set of parameters.