An SAR ADC Using A New Type of Logical Algorithm

A 12-bit successive-approximation-register analog-to-digital converter (SAR ADC) was designed in SMIC 40nm CMOS process. Base on traditional SAR logic, add an algorithm of when analog input signal changes slowly, ADC locking its first 4 bits, and only do last 8 conversions. And when analog input signal has great change, ADC returns to normal working mode. It decreases power consumption and increase sampling rate of ADC, but doesn't change resolution of ADC. Under a 1.1V supply and 3.6 MS/s sampling rate, the total power consumption of ADC is 43 μW, and the FOM is 10.1fJ/(conv.·step).