Implementation with FPGA Based on IQ for AVS Decoding

Analysising the mudule of the AVS inverse quantization, a method of using less Rom to save data in Quantization Table is proposed in this paper. Through the preparation of VHDL in order to implement the optimized inverse algorithm for AVS decoding, By means of the FPGA tool ISE7.1 and ModelSim SE 6.0, inverse quantization for AVS decoding base on FPGA can be implemented. The result of simulation is given in this paper which the Validity of the algorithm has been proved.