A Design of DES IP Core Based on AHB Bus

LIU Mu-xuan, ZHANG Shu-dan, TANG Cai-bin. A Design of DES IP Core Based on AHB Bus[J]. Microelectronics & Computer, 2014, 31(10): 69-71.

Citation:

LIU Mu-xuan, ZHANG Shu-dan, TANG Cai-bin. A Design of DES IP Core Based on AHB Bus[J]. Microelectronics & Computer, 2014, 31(10): 69-71.

Citation:

LIU Mu-xuan, ZHANG Shu-dan, TANG Cai-bin. A Design of DES IP Core Based on AHB Bus[J]. Microelectronics & Computer, 2014, 31(10): 69-71.

Abstract

This paper presents a DES IP core equipped with a AHB Slave Interface.It works perfectly with a bus frequency of 500 MHz.The maximum sustained conversion rate for DES is around 1.6Gb/s.And it is around 615Mb/s for 3DES.After simulating by VCS and synthesizing by DC,results show that it fulfills the design require.

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