A High Performance Hardware Design for HEVC Integral Motion Estimation

In this paper, a motion estimation algorithm suitable for hardware implementation is proposed for integer motion estimation, and the hardware architecture is also presented. By reusing computing unit in the CU depths, the hardware resource is greatly reduced. Synthesized results in the TSMC 90nm show that the frequency of presented architecture can reach 377 MHz and the throughput can achieve 3 840×2 160@60 f/s real-time processing in the search range of ±64, which meets the requirement of processing HD video images in real time.