Design of high speed serial transmission system for multiprocessor interconnects

In order to deal with the real-time processing of large data volume, and to solve the communication bandwidth bottleneck between processors, a high-speed serial transmission system for the interconnection of new RISC-V processors was built by self-developed hybrid multi-FPGA platform. It has achieved a single-channel 4x transmission rate improvement. Experiments show that the total throughput rate of the system can reach 300 Gbps, the single channel rate can reach 25 Gbps, the supported interconnect links are greater than 40, and the transmission error rate is less than 1E -11, which can meet most high-bandwidth and high-reliability transmission requirements, greatly reducing the number of IO pins. Finally, based on this system, at the same rate, compare and evaluate the implementation of three high-speed serial protocols, To help improve transmission efficiency and system optimization.