Intelligent target detection algorithm for embedded FPGA

With the improvement of recognition rate and real-time performance, the computational complexity and memory requirements of convolutional neural network target detection algorithm increase sharply, which makes it difficult to be applied to embedded platform with small size and low power consumption. In this paper, based on the analysis of the existing neural network model structure of target detection, according to the characteristics of high real-time performance, low power consumption and parallel processing of FPGA, a neural network model normalization method based on high speed operation on FPGA is proposed. Under the guidance of this method, a target detection neural network model structure is designed and implemented, including removing the LRN layer, fusion of Scale layer and replacing Leaky-ReLU with ReLU. The effectiveness of the proposed algorithm structure is verified by comparative experiments on VOC2007 dataset. Compared with traditional YOLO-V1 algorithm, the speed of the proposed algorithm on PC is improved by 11.5%. Hardware simulation under Xilinx ZCU102 shows that the improved target detection algorithm can reach the speed of 29FPS (Frames Per Second) and the accuracy of 62.3mAP.