Design of a 12-bit 1000MSPS CMOS Sample and Hold Circuit

A 12bit 100 MSPS pipelined analog--to digital converter (ADC) sample and hold circuit is designed based 0. 13μm/3. 3V CMOS process. In this circuit, a high linearity Double Side Symmetrical No Feed Through (DSSNFT) bootstrapped switch, a high gain wide bandwidth Cascode Transconductance Feed Forward (CTFF) compensation two-stage fully differential OTA and a low gain--error correlated double sampling S/H topology structure are used to build S/H circuit. The simulation results show that SFDR can reach 86. 4dB with input signal 11.27MHz and sample signal 111MHz. Power consumption is about 32mW at a 3.3V supply.