Design of Low Energy Consumption 3-Input AND/XOR Gate

A transmission gate logic based low energy consumption 3-input AND/XOR gate is proposed. Under 55 nm CMOS process, the post-simulations of the circuit under different process corners are carried out by using HSPICE and compared with the published circuits. The simulation results show that the performance of this circuit is good, under typical process corner, the improvement of the proposed circuit can be up to 10.08%, 29.03% and 36.12% respectively in terms of the power, delay and power delay product, which meets the design requirement of low energy.