Vertex Shader Processor Design Based on Very Long Instruction Word

In order to improve the vertex shader processor in the Graphic Process Unit (GPU), a programmable vertex shader processor with a very long instruction word format is designed and implemented in a six-stage pipeline. Each instruction has a maximum of one cycle Implementation of seven kinds of operations, hardware and software co-design, reducing power consumption. Using FPGA-based verification, the programmable vertex shader processor achieves a maximum operating frequency of 50 MHz on the Xilinx Virtex-7 FPGAs V2000T, a vertex processing speed of 0.16 M/s, and an average of 44 cycles for a vertex. At Synopsys Design Compiler tools 130 μm process synthesis, clocked at 150 MHz, power consumption is about 177.7428 mW.