Design of an 11-Bit Pipelined ADC with Improved OPAMP Sharing Configuration

This paper presents the improvement of the OPAMP sharing configuration for the pipelined analog to digital converter (ADC), and designs an 11-bit and 100 MS/s sampling-rate pipeline ADC for a UHF RFID system. The sample and hold circuit shares the same OPAMP with the first-stage residual gain amplifier circuit, so that current efficiency of OPAMP is improved and power consumption is saved. The OPAMP adopts gain-boost telescope structure with two pairs input and one pair output. By using symmetrical bootstrapped switch, the charge injection mismatch is reduced, when large current flows into virtual ground. The pipeline ADC achieves an ENOB of 10.6 bits, an SFDR of 71.2 dB, an SNDR of 65.5 dB and power consumption of 52 mW at the Nyquist sampling input frequency.