YAN Yuan-hai, SHI Hong-sheng, KANG Kai, HU Ze-min. DSP Implementation of Binary BCH Encoding and Decoding[J]. Microelectronics & Computer, 2018, 35(8): 64-67.
Citation: YAN Yuan-hai, SHI Hong-sheng, KANG Kai, HU Ze-min. DSP Implementation of Binary BCH Encoding and Decoding[J]. Microelectronics & Computer, 2018, 35(8): 64-67.

DSP Implementation of Binary BCH Encoding and Decoding

  • Aiming at the wireless communication between DSP hardware, a binary BCH (15, 7) codec based on DSP is proposed. Designed by TI's 32-bit floating point high-performance DSP processor, through the CCS software platform, respectively, prepared the corresponding coding, decoding and error correction procedures. In this paper, the algorithm of binary BCH (15, 7) code and its error correction code is introduced, and the corresponding C language program is given. Through the serial communication between DSP and PC, BCH coding and decoding and error correction function are verified. When the DSP receive data is less than or equal to two random errors, you can find the error and give correction. Compared with the FPGA, while ensuring the accuracy of data transmission at the same time, reducing the cost of hardware, simplifying the difficulty of the algorithm.
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